Generally, a power-on reset circuit generates a reset pulse upon power on to allow certain logic to enter a predetermined state. Because the power-on reset circuit is typically operated without use of an external power supply pin, it is mostly employed in integrated circuits.
Various considerations must be accounted for when implementing a power-on reset circuit. First, the rise time of a voltage V.sub.DD being charged in the integrated circuit after power-on is varied according to the size and characteristics of the integrated circuit. The power-on reset circuit must generate a reset clock pulse upon power-up to reset the logic in the integrated circuit regardless of the rise time of the voltage V.sub.DD, so as to allow the logic to enter an operable state.
Second, the power-on reset circuit must consume little or no power when in a stable state after generation of a reset signal. Third, the power-on reset circuit must occupy very little space within the integrated circuit.
However, in a conventional power-on reset circuit, the reset operation is generally performed by delaying a reset state prior to power-on, typically using a time delay device comprising a resistor and a capacitor. This results in the release of the reset state before power-up of the integrated circuit in cases where the voltage V.sub.DD rise time is long. Also, a conventional power-on reset circuit generally continues to consume an appreciable amount of power after generation of the reset signal and occupies a considerable amount of space within the integrated circuit, resulting in reduced levels of integration and integration flexibility.